Ttihp Dual Sram

B 83 completed
Other
containerized / vlang · tiny
46
Files
41,165
LOC
1
Frameworks
7
Languages

Pipeline State

completed
Run ID
#370393
Phase
done
Progress
1%
Started
Finished
2026-04-13 01:31:02
LLM tokens
0

Pipeline Metadata

Stage
Cataloged
Decision
proceed
Novelty
72.00
Framework unique
Isolation
Last stage change
2026-05-10 03:34:51
Deduplication group #54694
Member of a group with 1 similar repo(s) — this repo is canonical view group →
Top concepts (2)
Project DescriptionTesting
Repobility · open methodology · https://repobility.com/research/

AI Prompt

Create a template for a dual-port SRAM module designed for Tiny Tapeout ASIC designs. The project should include necessary Verilog source files, a testbench, and documentation. I need to know how to set up the project by editing `info.yaml` to specify `source_files` and `top_module`, and how to adapt the testbench. The structure should support automated ASIC file building using OpenLane via GitHub actions.
verilog asic sram hardware design tiny-tapeout testbench yaml electronics
Generated by gemma4:latest

Catalog Information

This project provides a dual‑port SRAM module template for Tiny Tapeout ASIC designs, including Verilog source, testbench, and documentation.

Description

The design implements a dual‑port SRAM that can be integrated into custom ASICs. It includes a complete Verilog implementation, a comprehensive testbench, and detailed documentation to guide users through configuration and verification. The module supports simultaneous read and write operations on two independent ports, making it suitable for high‑throughput applications. It is intended for hardware designers and students who need a ready‑made memory block for educational or prototyping purposes. The project also serves as a starting point for further customization and optimization in ASIC development workflows.

الوصف

يُقدّم التصميم وحدة ذاكرة SRAM ذات منفذين يمكن دمجها في شريحة ASIC مخصصة. يتضمن المشروع تنفيذًا كاملاً بلغة Verilog، وبيانات اختبار شاملة، ووثائق مفصلة لتوجيه المستخدمين عبر التكوين والتحقق. تدعم الوحدة عمليات القراءة والكتابة المتزامنة على منفذين مستقلين، ما يجعلها مناسبة لتطبيقات ذات معدل نقل عالٍ. يُستهدف هذا المشروع المصممين الميكانيكيين والطلاب الذين يحتاجون إلى كتلة ذاكرة جاهزة للاستخدام في التعليم أو النمذجة الأولية. كما يُعد نقطة انطلاق لتخصيص وتحسين أكثر في عمليات تطوير ASIC. يشتمل المشروع على دليل خطوة بخطوة لتعديل ملفات المصدر وتحديث ملفات التكوين. يتيح وجود بيانات اختبار متكاملة للمستخدمين التحقق من صحة الأداء قبل الانتقال إلى الإنتاج.

Novelty

3/10

Tags

dual-port-sram asic-design chip-fabrication digital-logic hardware-template educational testbench design-documentation

Claude Models

claude-opus-4.6

Quality Score

B
83.3/100
Structure
77
Code Quality
100
Documentation
56
Testing
85
Practices
78
Security
100
Dependencies
50

Strengths

  • CI/CD pipeline configured (github_actions)
  • Good test coverage (200% test-to-source ratio)
  • Consistent naming conventions (snake_case)
  • Low average code complexity \u2014 well-structured code
  • Good security practices \u2014 no major issues detected
  • Containerized deployment (Docker)
  • Properly licensed project

Recommendations

  • Add a linter configuration to enforce code style consistency

Security & Health

4.1h
Tech Debt (A)
A
OWASP (100%)
PASS
Quality Gate
A
Risk (0)
Want fix-PRs on findings? Install Repobility's GitHub App · github.com/apps/repobility-bot
Apache-2.0
License
11.1%
Duplication
Full Security Report AI Fix Prompts SARIF SBOM

Languages

vlang
48.6%
json
19.3%
yaml
13.8%
python
13.1%
markdown
4.8%
shell
0.4%
text
0.2%

Frameworks

pytest

Concepts (2)

Repobility analysis · methodology at https://repobility.com/research/
CategoryNameDescriptionConfidence
Same scanner, your repo: https://repobility.com — Repobility
auto_descriptionProject Description- Read the documentation for project80%
auto_categoryTestingtesting70%

Quality Timeline

1 quality score recorded.

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